1. Field of the Invention
The present invention relates to a semiconductor device.
2. Description of the Related Art
In a semiconductor device such as a conventional dynamic random access memory (DRAM), there has been known a hierarchical bit line structure in which a plurality of sub bit lines are provided for each of main bit lines. See, e.g., Japanese Unexamined Patent Application Publication (JP-A) No. 2009-33029 (Patent Literature 1).
Patent Literature 1 discloses a semiconductor device having a hierarchical bit line structure in which for adjacent main bit lines, main bit lines (MBL0-MBLn) are provided in a second metal wiring layer and the other main bit line (/MBL0-/MBLn) are provided in a third metal wiring layer, in order to prevent an initial differential potential to be inputted into a sense amplifier from being lowered due to an increase of a side coupling capacitance between the adjacent main bit lines, which is caused when wiring pitches (the sum of the line width and the space width of the wiring layers) are reduced. Specifically, in the semiconductor device disclosed in Patent Literature 1, main bit lines that are arranged adjacent to each other on a plane are provided in different layers, thereby preventing an increase of the side coupling capacitance between those main bit lines.
The semiconductor device disclosed in Patent Literature 1 suffers from a problem that a difference is produced in capacitance between the main bit lines MBL0-MBLn provided in the second metal wiring layer and the main bit lines /MBL0-/MBLn provided in the third metal wiring layer. For example, as shown in FIG. 4 of Patent Literature 1, each of the main bit lines MBL0-MBLn provided in the second metal wiring layer has a side coupling capacitance Cc2a between the main bit lines MBL and a capacitance between the main bit line and a wire (sub bit line SBL) provided in a first metal wiring layer located below the second metal wiring layer.
Each of the main bit lines /MBL0-/MBLn provided in the third metal wiring layer has a side coupling capacitance Cc3a between the main bit lines /MBL and a capacitance between the main bit line and a wire (word line WL) provided in a fourth metal wiring layer located above the third metal wiring layer. Therefore, the capacitance of the main bit lines MBL0-MBLn provided in the second metal wiring layer becomes different from the capacitance of the main bit lines /MBL0-/MBLn provided in the third metal wiring layer. Thus, a difference is produced in capacitance between the main bit lines.
As a result of the difference in capacitance between the main bit lines, upon reading data in the semiconductor device, initial potentials generated by data read from memory cells may vary between the main bit lines provided in the second metal wiring layer and the main bit lines provided in the third metal wiring layer.
Variations of the initial potentials make it difficult to match operation margins of sense amplifiers connected to the main bit lines provided in the second metal wiring layer with operation margins of sense amplifiers connected to the main bit lines provided in the third metal wiring layer. Therefore, it becomes difficult to design sense amplifiers as an operation speed of the semiconductor device increases.